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MRF49XA
3.3
Power and Low Noise Amplifiers
TABLE 3-1:
PROGRAMMABLE LOAD
CAP1
CAP0
The PA is an open-collector, differential output with
programmable output power which can directly drive a
loop or dipole antenna, and with proper matching, can
CAP3
CAP2
CAPACITANCE VALUE
Load
Capacitance
also drive a monopole antenna. An automatic antenna
tuning circuit configured in the PA avoids the manual
tuning during production and this offsets “hand effects”.
The registers associated with the PA are:
? TXCREG (see Register 2-4 )
? PMCREG (see Register 2-13 )
The input LNA has selectable gain (0 dB, -6 dB, -14 dB
and -20 dB) which is useful in environments with strong
interferers. The LNA has 250 ? of differential input
impedance, which requires a matching circuit when
connected to 50 ? devices.
The registers associated with the LNA are:
? RXCREG (see Register 2-7 )
? PMCREG (see Register 2-13 )
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
3.4
Crystal Oscillator and Clock
Output
1
1
1
1
0
1
1
0
15
15.5
The MRF49XA has a single pin crystal oscillator circuit,
which provides a 10 MHz reference signal for the
on-chip PLL. The clock frequency is programmable from
eight predefined frequencies, each being a prescaled
value of a 10 MHz crystal reference. A programmable
crystal load capacitor has been internally configured to
reduce the external component count and to have a
much simplified design. The internal load capacitor is
programmable from 8.5 pF – 16 pF in 0.5 pF steps as
defined GENCREG. This provides the advantage of
1 1 1 1 16
The crystal oscillator provides a reference signal to the
RF synthesizer, baseband circuits and digital signal
processing parts. If receiver or transmitter blocks are
used frequently, it is recommended to leave the
oscillator running because the crystal might need a few
milliseconds to start and stabilize. The stabilization
time mainly depends on the crystal parameters.
The CLKOEN bit (PMCREG<0>) is used to enable or
disable the clock output.
accepting a wide range of crystals from different
manufacturers with different load capacitance
3.4.1
CLOCK TAIL FEATURE
requirements. For load capacitance values, see
Table 3-1. These values are programmable through the
BCSREG (see Register 2-16 ).
The crystal oscillator circuit is sensitive to parasitic
capacitance for start-up. A small amount of parasitic
capacitance is needed to facilitate oscillation. To achieve
this, create a ground plane around the crystal and widen
the connection to the MRF49XA. This is to adjust the
reference frequency and to compensate for stray
capacitance that might be introduced due to PCB layout.
If the layout is not possible, a 0.5 pF – 1 pF capacitor,
soldered across the crystal, will initiate the start-up. Also,
see Section 3.6, Crystal Selection Guidelines for
The MRF49XA provides the clock signal for the
microcontroller for accurate timing, and thus, removes
the need for a second crystal for any board design.
When the microcontroller turns off the crystal oscillator
by clearing the OSCEN bit (PMCREG<3>), the
MRF49XA provides a fixed number (192) of further clock
pulses for the microcontroller to switch itself to Idle or
Sleep mode (Low-Power Consumption modes). To use
this feature, STSREG must be read before the OSCEN
bit is set to ‘ 0 ’. If STSREG is not read, then the clock
output will not shut down. If the CLKOUT pin is not used,
it is suggested to turn off the output buffer from
PMCREG.
selecting the right crystal.
Note:
Leaving blocks needlessly turned on
increases the current consumption, and
thus, reduces the battery life.
The microcontroller clock source (if the clock is not
supplied by the MRF49XA) should be stable enough
over temperature and voltage ranges to ensure a
minimum of 16 bits time delay under all operating
circumstances.
? 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 47
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